What will you do?

We are looking for an experienced engineer/ engineer ASIC to join our innovative team to define and deliver Testchips to take new technology paths. You will participate in the definition and design of the protester testing with a focus on memory techniques from the next generation. You will interact with the teams of the device, integration, and the system/DTCO teams to pay projects from the concept to the silicone tape in close cooperation with different teams (the device, integration, corresponding design, test, …)

You will be responsible for:

• Detharam definition test, specifications, and planning.
• Integration of physical design (including flooring plan) and coordination of login in the sub -system and full chips level.
• RTL design, selection and integration.
• Definition of the verification, measurement and description strategy, including testing structures (DFT, BIST, …) and agreements with the test team.

What do we do for you

• Full -time position in IMEC Leuven, Belgium or IMEC Cambridge, UK.
• An exciting position in a multidisciplinary team.
• An opportunity to interact closely with circuit designers, hardware experts and operations integration engineers.
• High effect and vision through publications and interactions with Fabless, Fables and EDA main partners.

We provide you with the opportunity to join one of the world’s leading research centers in nanotechnology. With your talent, passion and experience, you will become part of a team that makes the impossible possible. Together, we form the technology that will determine tomorrow’s society.

We are committed to being a comprehensive and proud business owner of the open, multi -cultural and informal work environment with wide capabilities to take the initiative and show responsibility. We adhere to support and direct you in this process; Not only with words but also with concrete procedures. Through IMEC.ACADY, “Our Companies University”, we actively invest in your development to enhance technical and personal growth.

We realize that your valuable contribution makes Imec the best player in its field. Therefore, your energy and commitment are estimated by the appropriate salary for the market with many marginal benefits.

Who are you

• The ideal candidate will have a master’s degree in electronics with industrial or academic experience relevant at least 5 years in the design of circles.
• You have the design of digital and rear circuits actual implementation at the highest level.
• You have experience in a chip test, a demonstratory definition, and the driving of the tape.
• You have an understanding of the basic performance and the characteristics of emerging memories.
• You have a good understanding of the division on the chip, record, and design structures for the test.
• You are efficient either with EDA rhythm/summary tools and flows.
• You are familiar with the anchors of the measuring equipment. You can understand their restrictions and take into account your design for the test strategy.
• Experience with PCB, design plate design or FPGA programming is plus.
• Experience with automatic or semi -automatic investigation stations, manual investigation measurement and concepts on investigation pillow layouts and the design of the Probecard card is plus.
• I have worked in multidisciplinary teams, perfectly, interacting with devices designers as well as EDA sellers and Foundry partners.
• You have a critical mindset, keen to explore new challenges in the future and develop with changing research and development requirements.
• You are an open and constructive team player. Lead team experience is plus.

What will you do?

We are looking for an experienced engineer/ engineer ASIC to join our innovative team to define and deliver Testchips to take new technology paths. You will participate in the definition and design of the protester testing with a focus on memory techniques from the next generation. You will interact with the teams of the device, integration, and the system/DTCO teams to pay projects from the concept to the silicone tape in close cooperation with different teams (the device, integration, corresponding design, test, …)

You will be responsible for:

• Detharam definition test, specifications, and planning.
• Integration of physical design (including flooring plan) and coordination of login in the sub -system and full chips level.
• RTL design, selection and integration.
• Definition of the verification, measurement and description strategy, including testing structures (DFT, BIST, …) and agreements with the test team.

What do we do for you

• Full -time position in IMEC Leuven, Belgium or IMEC Cambridge, UK.
• An exciting position in a multidisciplinary team.
• An opportunity to interact closely with circuit designers, hardware experts and operations integration engineers.
• High effect and vision through publications and interactions with Fabless, Fables and EDA main partners.

We provide you with the opportunity to join one of the world’s leading research centers in nanotechnology. With your talent, passion and experience, you will become part of a team that makes the impossible possible. Together, we form the technology that will determine tomorrow’s society.

We are committed to being a comprehensive and proud business owner of the open, multi -cultural and informal work environment with wide capabilities to take the initiative and show responsibility. We adhere to support and direct you in this process; Not only with words but also with concrete procedures. Through IMEC.ACADY, “Our Companies University”, we actively invest in your development to enhance technical and personal growth.

We realize that your valuable contribution makes Imec the best player in its field. Therefore, your energy and commitment are estimated by the appropriate salary for the market with many marginal benefits.

Who are you

• The ideal candidate will have a master’s degree in electronics with industrial or academic experience relevant at least 5 years in the design of circles.
• You have the design of digital and rear circuits actual implementation at the highest level.
• You have experience in a chip test, a demonstratory definition, and the driving of the tape.
• You have an understanding of the basic performance and the characteristics of emerging memories.
• You have a good understanding of the division on the chip, record, and design structures for the test.
• You are efficient either with EDA rhythm/summary tools and flows.
• You are familiar with the anchors of the measuring equipment. You can understand their restrictions and take into account your design for the test strategy.
• Experience with PCB, design plate design or FPGA programming is plus.
• Experience with automatic or semi -automatic investigation stations, manual investigation measurement and concepts on investigation pillow layouts and the design of the Probecard card is plus.
• I have worked in multidisciplinary teams, perfectly, interacting with devices designers as well as EDA sellers and Foundry partners.
• You have a critical mindset, keen to explore new challenges in the future and develop with changing research and development requirements.
• You are an open and constructive team player. Lead team experience is plus.